Publication: AN INVESTIGATION OF PARALLEL MEMETIC ALGORITHMS FOR VLSI CIRCUIT PARTITIONING ON MULTI-CORE COMPUTERS

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Title	AN INVESTIGATION OF PARALLEL MEMETIC ALGORITHMS FOR VLSI CIRCUIT PARTITIONING ON MULTI-CORE COMPUTERS
Authors/Editors*	E. Armstrong, G. Grewal, S. Areibi, G. Darlington
Where published*	IEEE Canadian Conference on Electrical and Computer Engineering
How published*	Proceedings
Year*	2010
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Pages
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Keywords	Memetic Algorithms; Circuit Partitioning; Computer Aided Design
Link	http://deimos.eos.uoguelph.ca/sareibi/PUBLICATIONS_dr/conferences/ccece10.pdf
Abstract	Circuit-partitioning is one of the most important, but time-consuming steps, in the VLSI design flow. In this paper, we investigate six different parallel Memetic Algorithms for solving the circuit-partitioning problem. Each parallel implementation uses a global shared-memory to exchange information, and seeks to reduce runtime by exploiting the multiple cores available in todayâs commodity hardware. When tested with the widely used ACM/SIGDA benchmark suite [16], our empirical results show that near-linear speedups for all six MAs can be achieved, while still producing high-quality solutions.