Publication: Design and FPGA Implementation of Min-Sum Algorithm and Its Variants

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Title Design and FPGA Implementation of Min-Sum Algorithm and Its Variants
Authors/Editors* S. Tolouei
Where published* M.Sc. Thesis at Carleton University
How published* Thesis
Year* 2007
In this thesis, the Min-Sum (MS) algorithm and its modified versions are studied. We study the effects of clipping and quantization on the performance of the successive relaxation min-sum (SR-MS) algorithm. We compare SR-MS with the modified MS algorithm with unconditional correction, known to be one of the best iterative algorithms in terms of performance/complexity tradeoff. We demonstrate that the optimal clipping threshold for SR-MS is a function of the code and in general increases with SNR and the number of quantization bits. For practical proposes however, the optimal clipping threshold can be assumed constant over a relatively small range of SNR values of interest. We also show that for the tested codes, SR-MS with 7-bit quantization outperforms floating-point belief propagation (BP) algorithm, particularly at high SNR values. This is while unlike BP, SR-MS does not require an estimate of SNR. To verify the performance of the proposed modification in comparison with quantized MS and MS with unconditional correction, we implement the three algorithms on a Virtex-II Pro FPGA. The circuit utilization and throughput of the 4-bit quantized MS algorithm with its modified versions are compared. We show that for MS with unconditional correction, the circuit utilization increases by 2% and the throughput is the same as that of MS. Also, the results for SR-MS implementation show that the device utilization is increased by 22% and the throughput is decreased by 20%.
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