Computing with Intel Xeon Phi Co-processor

Description

This training course will provide an introduction covering the basic knowledge needed to accelerate your programs by taking advantage of Intel Xeon Phi Co-processor which is a new and very prospective technology being used in the world’s largest supercomputer now. This course will focus on the Intel Many Integrated Core (MIC) hardware architecture, programming models and optimization techniques. The execution modes including native, offloading and heterogeneous will be discussed in detail with OpenMP, MPI, MKL and OpenCL examples. Students will learn to port and optimize their programs with an understanding of MIC’s hardware threads, vectorization and cache/memory layout. Hands-on exercises will also be given during the course.

Instructor: Fei Mao, SHARCNET, University of Guelph

Prerequisites: C/C++ or Fortran programming. We highly recommend you to attend at least one of our parallel programming courses (OpenMP, MPI or CUDA) before this course.

*Please email the course instructor if you want to take the course but are not sure you satisfy the pre-requisites.